1. Field of the Invention
This invention relates to R-S latches and in particular to an R-S latch which has no indeterminate state for any binary logic input signal condition.
2. Description of the Prior Art
R-S latches are well known and also may be known as R-S bistable multivibrators or R-S flip-flops. For a discussion of R-S flip-flops, reference should be made to the text, "Introduction to Switching Theory and Logical Design," Hill, F. J. And Peterson, G. R. John Wiley & Sons, Inc., second ed., pp. 213 - 215, which is incorporated herein by reference. As explained in the reference, a pulse on the S-input will "set" the flip-flop, i.e., drive the Q-output to the H or 1 level and the Q-output to the L or 0 level. A pulse on the (clear) reset line will reset the flip-flop, i.e., drive the Q-output to the L or 0 level and the Q-output to the H or 1 level. A problem occurs with the R-S latch (flip-flop) if a pulse should be applied to both at the same time. Thus, in normal operation, R-S flip-flops (latches) of the prior art necessarily required that both the R and S inputs should not be permitted to have pulses applied to both inputs at the same time. The rationale is: (1) if pulses are applied to both inputs, both outputs will be driven to 0, which violates the basic definition of flip-flop operation, which definition requires that the output should always be the complements of each other; and (2) if both inputs have pulses applied and the pulses are removed at the same time, the prior-art R-S latch will try to make both outputs equal to 1. Because of feedback it is not possible for both outputs to go to 1 at the same time. Thus, the flip-flop (latch) output is not predictable and may even oscillate.
These disadvantages are partially overcome by the circuit disclosed and claimed in U.S. Pat. No. 3,895,240 entitled, "Set Preferring R-S Flip-Flop Circuit." Here the circuit is identified as an R-S-S flip-flop circuit. The R-S-S is suited for use in which both R and S inputs may become 1 at the same time. Since on such an occurrence the set input is given preference, the output is not indeterminate as would occur with a standard R-S flip-flop. Thus, there is no need to inhibit the occurrence of simultaneous pulse inputs to this R-S-S latch. Such a circuit operates on the leading edge or positive transition of the input state(s), and on the occurrence of simultaneous pulse inputs the circuit will always return to the set state.